High-speed digital integrated circuit microprocessors and memories formed as semiconductor die (or integrated circuit chips) require multiple decoupling capacitors to aid in eliminating high-speed transient noise, and other circuit induced problems. For example, where high-speed transient noise is above a resonance point, inductive resistance forms a major impedance. As a result, decoupling capacitors are physically placed as close as possible to the semiconductor die, i.e., integrated circuit, and in particular, to any of its logic pins.
Many of these decoupling capacitors are discrete ceramic subassemblies having electrodes, a ceramic layer and terminated edge. They use wire connects and long path lengths from the decoupling capacitor positioned outside the periphery of the semiconductor die. This long length increases the equivalent series resistance (ESR) and equivalent series inductance (ESL). The equivalent series resistance is increased because the resistance of the capacitor leads in series with the equivalent resistance of the capacitor plates increases and causes the capacitor to dissipate power and produce loss when various currents are flowing. This is detrimental at various radio frequencies. The equivalent series inductance models any inductance of capacitor leads in series with the equivalent inductance of capacitor plates.
FIG. 1 shows a prior art multi-chip module (MCM) 10 or other semiconductor structure, e.g., integrated circuit chip module, where three semiconductor die (or chips) 14 with adjacent substrate bonding pads 20 are positioned on a substrate 12, such as a multilayer ceramic substrate formed from green tape sheets. A typical logic pin 18 placement is illustrated for the three semiconductor die. Decoupling capacitors 16 are positioned outside the peripheral boundary defined by the semiconductor die, as illustrated. Other thick film capacitors or other semiconductor devices 24 are printed or surface mounted in close proximity to the semiconductor die. The dimensional footprint imposed by the decoupling capacitors and the other semiconductor devices on the substrate adds severe dimensional restrictions, limiting additional structures. Also, because of the dimension restrictions, smaller decoupling capacitors, capacitors, and other semiconductor devices must be used, which could decrease reliability and reduce overall capacitance. FIG. 1 illustrates the typical wire bond or substrate trace 22 routing length from a substrate bond pad to the nearest decoupling capacitor. This long length is indicative of how the longer interconnect length could increase the equivalent series inductance and equivalent series resistance, degrading performance of the overall chip operation.
One prior art capacitor mounting technique is described in U.S. Pat. No. 5,377,072. A single, large metal plate bypass capacitor is stacked onto and substantially covers a silicon substrate that is separated by a thermally-grown silicon dioxide dielectric layer. Self-inductance of the bypass capacitor is minimized because the capacitor dielectric is formed as a very thin layer by the thermal oxidation of silicon. Bonding wires can be used to interconnect the plates of the bypass capacitor with the power and ground terminals in a semiconductor device, and enable minimal length bonding wires. Although there is some stacking and reduction of wire length, the structure is limited to a single metal-plate bypass capacitor that is large in dimension relative to the semiconductor device. This would not be adequate where a plurality of decoupling capacitors are required relative to a semiconductor die, such as an integrated circuit, where a minimal footprint is desired.